LSISASX12 LSI, LSISASX12 Datasheet - Page 106

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4068
Read/Write
4-28
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This Address Register 1 (AR1) is sent as the first byte in the address
phase of an API2C transaction.
R
I2CA1
AD
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Reserved
These bits are reserved.
API2C Address 1
These bits are sent as the first seven bits of the address
phase in an API2C transaction. If bits [7:3] equal 11110,
then 10-bit addressing is selected and bits [2:1] become
the two most significant bits of a 10-bit address. With 10-
bit addressing, an additional address byte is sent after
the access direction bit and the first address byte ACK.
The second byte is the lower eight bits of a 10-bit
address.
Access Direction
This bit is the API2C data direction bit. It is the eighth bit
sent after a start or repeated start condition.
AD
0
1
This bit is ignored when a Sequence Transfer command
is issued with the access direction automatically gener-
ated.
API2C Address Register 1
16 15
Function
Write Access. The data phase after the address phase
is taken from the Transmit FIFO and written to the
addressed slave.
Read Access. The data after the address phase is
returned by the addressed slave during the data phase.
The master state machine places the data in the
Receive FIFO.
8 7
0
0 0 0 0
[31:8]
0
[7:1]
0
0
0