LSISASX12 LSI, LSISASX12 Datasheet - Page 201

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LSISASX12

Manufacturer Part Number
LSISASX12
Description
Manufacturer
LSI
Datasheet

Specifications of LSISASX12

Lead Free Status / Rohs Status
Not Compliant

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STP Target Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
CRC Error Detected
The LSISASx12 sets this read-only bit when it detects a
bad CRC dword in a received FIS. The STP Target trans-
mits an R_ERR and leaves the connection open. The Ini-
tiator decides if to retransmit the failed FIS.
PMREQ Received
The LSISASx12 sets this read-only bit when it receives
either a PMREQ_P or PMREQ_S primitive. If this occurs,
the STP Target transmits PMNAK, and then transmits a
CLOSE sequence to close the connection.
R_RDY Timeout
The LSISASx12 sets this read-only bit if the STP Target
does not receive an R_RDY primitive within 1 ms after
transmitting X_RDY primitives. If this occurs, the STP Tar-
get transmits a CLOSE sequence to close the connec-
tion.
R_OK/R_ERR Timeout
The LSISASx12 sets this read-only bit if the STP Target
does not receive either an R_OK or R_ERR primitive
within 1 ms after transmitting an EOF/WTRM sequence.
If this occurs, the STP Target transmits a CLOSE
sequence to close the connection.
Unexpected SYNC
The LSISASx12 sets this read-only bit when the Link
Layer receives an unexpected SATA_SYNC primitive. The
Error Log – Unexpected SYNC Count
lative count of received unexpected SYNC primitives.
R_ERR Received
The LSISASx12 sets this read-only bit when it receives
an R_ERR in response to a DATA FIS, PIO Setup FIS, or
D2H Register FIS. The
ted/Received Count
R_ERR primitives that have been sent or received.
R_ERR Transmitted
The LSISASx12 sets this read-only bit when either the
Link Layer or Transport Layer detect a problem with a
received FIS that caused the Link Layer to assert
R_ERR. Bits [8:10] of this register provide the cause of
the error. The
Error Log – R_ERR Transmitted/Received
provides a cumulative count of
Error Log – R_ERR Transmit-
provides a cumu-
4-123
8
7
6
5
4
3
2

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