LSISASX12 LSI, LSISASX12 Datasheet - Page 55

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2.7.5
Figure 2.8
2.7.6
S
S
A
S
R
Master to Slave
Slave to Master
Control
Control
Control
Byte
Byte
Byte
Data_0
I
ATAPI Command Status
2
C Slave Read Operations
Slave Read Operation
W
W
R
A
A
A
A
Figure 2.8
header CRC byte follows the Address_Hi and Address_Lo bytes. The
header CRC is calculated using the control byte and the two address
bytes. The payload CRC byte follows the read data byte and is calculated
using only the read data byte.
For block read transfers, the header CRC byte follows the Address_Hi,
Address_Lo, and Byte_Count bytes. The header CRC is calculated using
the control byte and the two address bytes. The payload CRC byte
follows the last byte of read data, and is calculated using the read data
bytes only.
Table 2.10
These commands allow the EMB to access a bridge and to operate with
an ATAPI host.
STP Enclosure Management Interface
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
BLK=0 Addr_Hi
BLK=1 Addr_Hi
Payload CRC
S = Start Condition
P = Stop Condition
A = Acknowledge
R = Read
W = Write
Data_0
illustrates I
provides the expected results for common ATAPI commands.
A
A
A
A
P
Addr_Lo
Addr_Lo
Block Read
Byte Read
2
C read operations. For byte read transfers, the
A
A
A
Byte Count = n
Header CRC
Data_n
A
A
A
S
P
R
Header CRC
Payload CRC
Control
Byte
R
A
A
2-33
P