LSISASX12 LSI, LSISASX12 Datasheet - Page 221

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x509
Read/Write
Register: 0x600 - 0x603
Read/Write
7
0
7
0
0
0
EMB Slave Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
RR_Command0
0
0
Expected CRC
0
0
Expected CRC
When CRC checking is enabled and the LSISASx12
detects a CRC error, this register contains the value of
the header or payload CRC was expected. The
CRC
This register value remains latched until the CRC error is
cleared in the
RR_Command
These four registers contain the value to be presented
during the Command/Address phase on the register bus
interface. RR_Command0 contains the least-significant
byte of the command. RR_Command3 contains the
most-significant byte of the command.
-
RR_Command3
0
0
register contains the CRC value that was received.
0
0
Error Detection Control
0
0
0
0
0
0
register.
Actual
4-143
[7:0]
[7:0]