LSISASX12 LSI, LSISASX12 Datasheet - Page 70

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

3.3
Table 3.1
3-4
Signal Name
REFCLK
RTRIM
RX[11:0]+
RX[11:0]
TX[11:0]+
TX[11:0]
1. Boot load options configure the polarity of the RX+/RX signals and TX+/TX signals for
each phy through the
SAS/SATA Signals
1
1
1
1
SAS/SATA Signal Description
Table 3.1
Signal Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
BGA Position I/O
AC13, AB13
AA6
AC2, W3, P1,
L2, F2, C2,
C25, E25,
J25, N25,
V24, AB24
AC1, W2, N1,
L3, F3, B2,
C24, E24,
J24, N24,
V25, AB25
AC3, AA1, U1,
P2, G1, C1,
B26, G26,
L26, T25,
AA26, AC25
AC4, AB1, V1,
P3, H1, D1,
C26, H26,
M26, T24,
AB26, AC24
Phy Transmit Polarity
describes the SAS/SATA signals.
I
–
I
O
Description
The Reference Clock signal provides the serial
differential clock to the LSISASx12 expander. Connect a
75 MHz oscillator having an accuracy of at least 50 ppm
to these pins. To use a single-ended oscillator, REFCLK+
and REFCLK must be driven through a single-ended to
differential level-shifting network.
Refer to SEN S11054: LSISASx12 Design Considerations
(Document Number: DB05-000116-xx) for information
concerning this signal.
The Resistor Reference provides the analog resistor
reference for the GigaBlaze termination logic.
The Receive Differential Data signals provide the
differential data receiver for the respective phy[n].
The Transmit Differential Data signals provide the
differential data transmit signal for the respective phy[n].
and
Phy Receiver Polarity
registers.