LSISASX12 LSI, LSISASX12 Datasheet - Page 53

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

2.7.3
I
2
C Error Detection
Figure 2.6
Because the I
EMB transmits CRC bytes with each data transfer. The algorithm uses
an 8-bit CRC that is calculated using each byte in the data transfer,
including the control byte. The polynomial used for the CRC is:
x
Device users can enable or disable CRC checking by writing to the Error
Detection Control register. If CRC checking is disabled, then the
LSISASx12 still transmits CRC bytes during data transfers. CRC
checking is enabled by default after reset. When CRC checking is
STP Enclosure Management Interface
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
A7 A6
A7 A6
8
1
1
+ x
Device
Device
0
0
Type
Type
2
+ x + 1.
A5 A4
A5 A4
1
1
Control Byte
Control Byte
Pointer Low
Pointer Low
Address
Address
0
0
I
2
2
C bus is susceptible to errors in noisy environments, the
C Slave Addressing and Transfer Modes
A3
A3
A2
A2
Address
Address
Device
Device
A2 A1 A0
A2 A1 A0
A1 A0 W
A1 A0 W
W = 0
W = 0
Byte Transfers
Block Transfers
BLK = 0
BLK = 1
BLK
BLK
BC
7
BC
6
x
x
BC
5
x
x
Byte Count
BC
4
x
x
Pointer Hi
Pointer Hi
Address
Address
BC
A1
A1
3
1
1
BC
A1
A1
2
0
0
BC
A9
A9
1
BC
A8
A8
0
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