LSISASX12 LSI, LSISASX12 Datasheet - Page 215
LSISASX12
Manufacturer Part Number
LSISASX12
Description
Manufacturer
LSI
Datasheet
1.LSISASX12.pdf
(268 pages)
Specifications of LSISASX12
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LSISASX12A
Manufacturer:
LSILOGIC
Quantity:
5 510
Company:
Part Number:
LSISASX12A
Manufacturer:
LT
Quantity:
5 510
- Current page: 215 of 268
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Register: 0x501
Read/Write
7
0
0
EMB Slave Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
0
SEP - STP Doorbell
0
Reserved
SEP Aborted Command
This bit is set when an I
SEP is transferring data to or from the I
Command Status Ready
The SEP sets this bit to indicate that the Command Sta-
tus register has valid status information.
Read Data Ready
The SEP sets this bit to indicate that the Data FIS RAM
contains valid data for the STP target to transfer to the
host.
Write Data Acknowledge
The SEP sets this bit to indicate that the SEP has trans-
ferred the write data from the Data FIS RAM.
Reserved
PACKET Command ACK
This bit is set after a Packet data-in command is parsed
successfully. The Read Data Ready bit is used when a
Packet data-out command is received.
0
0
0
2
C CRC error occurs while the
0
0
2
C Slave.
4-137
[2:1]
7
6
5
4
3
0
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