LSISASX12 LSI, LSISASX12 Datasheet - Page 177

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

4.5
STP Target Registers
Table 4.10
EMB. Detailed bit descriptions follow the register map.
Table 4.10
STP Target Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
0x000–0x00C
0x018–0x40
Offset
0x04C
0x05C
0x06C
0x07C
0x010
0x014
0x044
0x048
0x050
0x054
0x058
0x060
0x064
0x068
0x070
0x074
0x078
0x080
0x084
0x088
provides the register map for the STP target portion of the
STP Target Register Map
JitterReg
When set to pattern 7, the jitter engine uses this value.
Use this field to generate a “clock” pattern of various fre-
quencies to assist in jitter measurements. The upper and
lower halves of this register are flipped prior to serializa-
tion, i.e. TxDataOut = {JitterReg[9:0],JitterReg[19:10]}.
Discover Information 4 – Attached SAS Address High
Discover Information 5 – Attached SAS Address Low
Discover Information 6 – Attached Phy Identifier
Discover Information 2 – SAS Address High
Discover Information 3 – SAS Address Low
Discover Information 9 – Routing Attributes
Discover Information 10 – Vendor Specific
Discover Information 8 – Link Rates
Discover Information 7 – Reserved
STP Target SAS Address High
STP Target SAS Address Low
Expander SAS Address High
Expander SAS Address Low
SATA Dev2Host Reset FIS0
SATA Dev2Host Reset FIS1
SATA Dev2Host Reset FIS2
Discover Information
Phy SATA Phy ID
Register Name
Reserved
Reserved
Reserved
Reserved
[19:0]
4-99