LSISASX12 LSI, LSISASX12 Datasheet - Page 95

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4000
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register independently enables the master unit and globally enables
and disables the IBML time-out timers.
R
IE
R
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
ISTWI Address
This read-only field provides the value of the ISTWI
address input pins. This is also referred to as the I
address.
Reserved
Phy Enable Bit Enable
This bit enables the Phy Enable bits in the
ration
Boot Start
Setting this write-only bit initiates a boot download oper-
ation. This bit is self-clearing.
Boot Stop
Setting this write-only bit aborts the boot download oper-
ation. This bit is self-clearing.
Reserved
These bits are reserved.
Timer Enable
This bit enables the API2Ctimers.
IE
0
1
Reserved
This bit is reserved and is hardwired to 0x0.
API2C Global Control
IBML Timers
register.
16 15
Disable
Enable
8 7
0
0 0 0 0
Phy Configu-
[17:16]
[15:3]
[31:3]
2
0
C
4-17
0
0
2
1
0
2
1