LSISASX12 LSI, LSISASX12 Datasheet - Page 117

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4118
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register sets up the clock based on the 75 MHz PCLK frequency. It
is configured automatically during system initialization. It is not necessary
to program this register.
This register controls the data setup time when the master is driving SCL
and SDA. The programmed value specifies the length of time that SDA
is stable prior to a rising edge on SCL. This value is in units of PCLK
cycles.
R
SDASC
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Note:
This register provides the t
API2C interface.
Reserved
These bits are reserved.
SDA Setup Count
This 16-bit programmed value loads into the counter
The 16-bit counter begins counting down on each PCLK
cycle. SCL is held LOW until the counter reaches 0.
Program an appropriate value for the desired speed
mode. The available modes are the standard mode or the
fast mode.
API2C Setup Time
Following an extension of the SCL LOW period by the
master state machine to hold the interface in a Wait
state (when SDA might change with new data)
When the master state machine is about to generate
a Stop condition (when both SCL and SDA might
change state)
16 15
SU:DAT
8 7
timing parameter for the
0
0 0 0 0
[31:16]
[15:0]
0
4-39
0
0