LSISASX12 LSI, LSISASX12 Datasheet - Page 118

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4120
Read/Write
4-40
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register sets up the clock based on the 75 MHz PCLK frequency. It
is configured automatically during system initialization. It is not necessary
to program this register.
This register controls the data hold time when the API2C core controls
the SDA signal. The programmed value specifies the length of time that
the SDA signal is stable following a falling edge on SCL. This value is in
units of PCLK cycles.
R
SDAHC
Register Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
Note:
This register provides the t
API2C interface.
Reserved
These bits are reserved.
SDA Hold Count
Whenever SDA transitions (from driven to not driven, or
from not driven to driven), this value loads into a 16-bit
counter that begins counting down on each PCLK cycle.
The transition is delayed until the counter reaches 0.
Program an appropriate value for the desired speed
mode. The available modes are the standard mode or the
fast mode.
API2C SDA Hold Time
16 15
HD:DAT
8 7
timing parameter for the
0
0 0 0 0
[31:16]
[15:0]
0
0
0