LSISASX12 LSI, LSISASX12 Datasheet - Page 109

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x4090
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RFD
This register enables the individual master state machine interrupts. The
bits in this register correspond to the interrupt status bits in the
Master Interrupt Status
registers are set to 1, the interrupt status is reflected on the external
interrupt signal and in the Master Interrupt bit in the
Interrupt Status
R
MIE
R
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
API2C Master Interrupt Enable
Receive FIFO Depth
This field indicates the current number of data bytes in
the Receive FIFO. A value of 0 means the Receive FIFO
is empty, while a value of 8 indicates the Receive FIFO
is full. The values of 9-15 are reserved.
Reserved
These bits are reserved.
Master Interrupt Enables
These bits enable the master interrupt status for the cor-
responding individual interrupt sources in the
Master Interrupt Status
MIE
0
1
Reserved
These bits are reserved and unused, but are writable.
register.
16 15
register. When corresponding bits in both
Function
Individual interrupt disabled.
Individual interrupt enabled.
register.
8 7
0
API2C Master
0 0 0 0
API2C
API2C
[31:16]
[15:4]
0
[3:0]
[3:0]
4-31
0
0