LSISASX12 LSI, LSISASX12 Datasheet - Page 147

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xC04C
Read/Write
Register: 0xC050
Read/Write
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
This register controls the enhanced SGPIO pattern definition on the
LSISASx12A expander. This register is not present on the LSISASx12
expander.
This register controls the enhanced SGPIO pattern definition on the
LSISASx12A expander. This register is not present on the LSISASx12
expander.
Configuration Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
Timebase 3
Clearing this bit causes the pattern to rotate at 40 Hz,
which provides an interval of 25 ms between each bit
shift. Setting this bit causes the pattern to rotate at 10 Hz,
which provides an interval of 100 ms between each bit
shift.
Reserved
Pattern 3
This field contains pattern 3. This pattern is sampled at
bits 0, 5, and 10 to allow for 0/90/180 phase shifts in the
output pattern.
SIO Pattern Definition 3
Activity Stretch Control
16 15
16 15
8 7
8 7
0
0
0 0 0 0
0 0 0 1
[30:20]
[19:0]
0
0
4-69
31
0
0
0
0