LSISASX12 LSI, LSISASX12 Datasheet - Page 219

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0x507
Read/Write
7
0
0
EMB Slave Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
0
Error Status
0
Transaction Type
This bit indicates the type of transaction in progress when
a CRC error or transfer length error occurred. The value
of this register bit remains latched until another error is
detected.
If a transfer length error occurred:
If a payload CRC error occurred, a value of 0 indicates a
WRITE transaction had a payload CRC error. (A payload
CRC error cannot be detected by the SEMB for a READ
transaction because the SEMB transmits the payload
CRC for READ transactions).
If a header CRC error occurred, this bit indicates the
value of the least-significant bit of the Control Byte for the
transfer that had the header CRC error.
Transfer Type
This bit indicates the type of transfer in progress when a
CRC error or Transfer Length error occurred. The value
remains latched until another error is detected.
If a payload CRC error or transfer length error occurred:
If a header CRC error occurred, this bit indicates the
value of the most-significant bit (BLK) of the Address
A value of 1 indicates a READ transaction had a
transfer length error.
A value of 0 indicates a WRITE transaction had a
transfer length error.
A value of 1 indicates a BLOCK transaction had the
error.
A value of 0 indicates a BYTE transaction had the
error.
0
0
0
0
0
4-141
7
6