LSISASX12 LSI, LSISASX12 Datasheet - Page 205

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Register: 0xn0
Read/Write
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4.12
The following provides descriptions of the phy configuration registers,
and the Global Configuration register.
This register provides per-phy configuration of arbitration and routing
attributes.
Expander Connection Manager Registers
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0x000D8–0x01FFF
0x000D0
0x000D4
0x02000
Offset
Connection Manager Phy Offsets (Cont.)
Reserved
Reserved
This bit is reserved for LSI Logic use. Clear this bit to 0b0
for normal operation.
Reserved
This bit is reserved for LSI Logic use. Clear this bit to 0b0
for normal operation.
Connect Wait
If the Partial Wait bit (bit 1 of this register) is set, then this
bit determines the action taken by the Connection Man-
ager when
Phy NN ECM Config
at least one destination matches the requested desti-
nation
no destinations that match are available, and
at least one of the destinations is connected.
16 15
SMP Target
SMP Target
Register Name
Global Config
Reserved
ECM Config
Remote Bank Enable
8 7
0
0 0 1 1
Register
[31:5]
1
4-127
0
0
4
3
2