LSISASX12 LSI, LSISASX12 Datasheet - Page 74

• Manufacturer Part Number: LSISASX12
• Manufacturer: LSI

Specifications of LSISASX12

• Lead Free Status / Rohs Status: Not Compliant

Table 3.5
3.8
3.9
Table 3.7
3-8
LSISASx12 Signal SIO Signal
LED_STATUS[10]/ SioClkin
LED_STATUS[11]/ SioClkout
LEDSYNCOUT
LEDSYNCIN
Signal Pin
IDDT
TN/
SCANMODE
JTAG Pins
Factory Test Pins
Multiplexed SIO Signals (Cont.)
Factory Test Pins
Ball
A2
E6
F19
BlinkClkin
BlinkClkout AF15
Table 3.6
Table 3.6
Table 3.7
reserved for LSI Logic test purposes.
Signal Descriptions
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Signal Name BGA Position I/O Description
TCK
TRST/
TDI
TDO
TMS
I
I
I
Type
describes the JTAG signal pins.
describes the factory test signal pins. These signals are
AF16
AE17
BGA
AF9
JTAG and Test Pins Signal Description
Description
Active HIGH IDDQ Test Mode Enable is for LSI Logic
production test only. Tie this pin to 0 for normal operation.
Used for LSI Logic production test only. Tie this signal to 1 for
normal operation.
Used for LSI Logic production test only.
E20
E19
D19
D18
E17
I/O
O
O
I
I
An originator with ClkEnable set to 1 in its SIO_CFG
register drives SioClkout as an output. The
ClkDivide bits in the SIO_CFG register control the
frequency of this clock. Originators with ClkEnable
cleared to 0 receive this clock signal on SioClkin.
An originator with ClkEnable set to 1 in its SIO_CFG
register drives BlinkClkout as an output with the
frequency fixed at 0.5 Hz. Originators with ClkEnable
cleared to 0 receive this clock signal on BlinkClkin.
O JTAG Debug test data out.
I
I
I
I
JTAG Debug clock.
JTAG Debug reset (active low).
JTAG Debug test data in.
JTAG Debug test mode select.
Description