n25q064 Numonyx, n25q064 Datasheet - Page 119

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q064 - 1.8V
9.3.15
9.3.16
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed.
The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The
instruction functionality is exactly the same as the Write Status Register (WRSR) instruction
of the Extended SPI protocol (See
the protection feature management is different. In particular, once SRWD bit is set to '1' the
device enters in the hardware protected mode (HPM) independently from Write Protect
(W/VPP) signal value. To exit the HPM mode is needed to switch temporarily to the
Extended SPI protocol.
Figure 92. Write Status Register instruction sequence QIO-SPI
Read Lock Register (RDLR)
The Read Lock Register instructions is used to read the lock register content. Apart from
parallelizing the instruction code, the address, and the output data on four pins (DQ0, DQ1,
DQ2, DQ3) the instruction functionality is the same as the Read Lock Register (RDLR)
instruction of the Extended SPI protocol. Refer to
(RDLR)
for further details.
DQ0
DQ3
DQ1
DQ2
S
C
Section 9.1.24: Write status register
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
5
4
6
7
Status Register In
3
1
0
2
3
Section 9.1.25: Read Lock Register
©2010 Micron Technology, Inc. All rights reserved.
(WRSR)). However,
Instructions
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