n25q064 Numonyx, n25q064 Datasheet - Page 92

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.2.5
9.2.6
92/154
DQ0
DQ1
C
S
0
Figure 48. Read OTP instruction and data-out sequence DIO-SPI
Instruction
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 49. Write Enable instruction sequence DIO-SPI
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the
Extended SPI protocol, please refer to
details.
Figure 50. Write Disable instruction sequence DIO-SPI
1
2
3
23 21 19 17
22 20 18 16
4
5
S
C
DQ0
DQ1
6
7
24-Bit Address
15 13 11 9
14 12 10 8
8
9 10 11
C
DQ0
DQ1
S
12 13 14 15
7
6
0
Instruction
5
4
1
3
2
2
1
0
3
0
Instruction
16 17 18 19 20 21 22 23 24 25 26 27 28
4
1
Section 9.1.11: Write Disable (WRDI)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
Dual_Write_Disable
Dummy cycles
3
4
7
MSB
6
Data Out 1
5
4
3
2
©2010 Micron Technology, Inc. All rights reserved.
1
0
MSB
6
7
Data Out n
4
5
2
3
N25Q064 - 1.8V
for further
0
1