n25q064 Numonyx, n25q064 Datasheet - Page 54

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
9.1
Note:
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Extended SPI Instructions
In Extended SPI protocol instruction set the instruction code is always shifted into the device
just on DQ0 pin, while depending on the instruction addresses and input/output data can run
on single, two or four wires.
In the case of a Read Instructions Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Dual Output Fast Read (DOFR), Dual Input/Output Fast Read (DIOFR),
Quad Output Fast Read (QOFR), Quad Input/Output Fast Read (QIOFR), Read OTP
(ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status
Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration
Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR), Read Serial
Flash Discovery Parameter (RDSFDP), and Read Identification (RDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be
driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP),
Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE),
Bulk Erase (BE), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write
to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced
Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write
Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That
is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array are ignored during:
The following continue unaffected, with one exception:
The only exception is the Program/Erase Suspend instruction (PES), that can be used to
pause all the program and the erase cycles except for:
The suspended program or erase cycle can be resumed by the Program/Erase Resume
instruction (PER). During the program/erase cycles, the polling instructions (both on the
Status register and on the Flag Status register) are also accepted to allow the application to
check the end of the internal modify cycles.
These polling instructions don't affect the internal cycles performing.
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Write Status Register cycle
Write Non Volatile Configuration Register
Program cycle
Erase cycle
Internal Write Status Register cycle,
Write Non Volatile Configuration Register,
Program cycle,
Erase cycle
Program OTP (POTP),
Bulk Erase,
Write Non Volatile Configuration Register.
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©2010 Micron Technology, Inc. All rights reserved.
N25Q064 - 1.8V