n25q064 Numonyx, n25q064 Datasheet - Page 67

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q064 - 1.8V
S
C
DQ0
S
C
DQ0
*Address bit A23 is “Don’t Care. ”
same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip
Select (S) must be driven Low for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes. See
Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is top) is initiated. While the Page Program cycle is in progress, the Status Register
and the Flag Status Register may be read to check if the internal modify cycle is finished. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP3,BP2, BP1, BP0 and TB) bits is not executed.
Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction
and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 21. Page Program Instruction Sequence
MSB
7
40
6
41
0
5
42
Data byte 2
1
4
43 44 45 46 47 48 49 50
2
Instruction
3
3
2
4
1
5
0
6
MSB
7
7
MSB
6
23
8
5
22 21
Data byte 3
9 10
24-bit address
4
51
3
52 53 54 55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
3
28 29 30 31 32 33 34 35
1
2
*
0
1
0
MSB
MSB
7
7
6
6
Data byte 256
5
5
Data byte 1
4
4
©2010 Micron Technology, Inc. All rights reserved.
3
3
36 37 38
2
2
Table 31.: AC
1
1
Page_Program
0
0
39
Instructions
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