n25q064 Numonyx, n25q064 Datasheet - Page 133

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q064 - 1.8V
10.3
DQ0
DQ3
DQ1
DQ2
Xb is the XIP Confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
*This bit is “Don’t Care.”
C
S
Mode 3
Mode 0
Table 24.
Figure 107. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)
XIP mode hold and exit
The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation
bit to be sent to the memory on DQ0 during the first dummy clock cycle.
The device decodes the XIP Confirmation bit with the scheme:
In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the
addresses is always Don't Care.
In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle
after the addresses are always Don't Care.
In Dual and Single I/O XIP mode, in presence of the RESET pin enabled (in devices with a
dedicated part number), a low pulse on that pin resets the XIP protocol as defined by the
Volatile Configuration Register, reporting the memory at the state of last power up, as
defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to
XIP Confirmation bit=0 means to hold XIP Mode
XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that
means codifying the first byte after the next chip select as an instruction code.
0
‘1’
Don’t Care
Don’t Care
1
81h (WRVCR opcode)
2
Instruction
VCR XIP bits setting example
3
4
5
6
7
A23-16 A15-8 A7-0
7*
4
5
6
8
2
3
0
1
9 10 11 12 13 14
4
5
6
7
2
3
0
1
6
7
4
5
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6 dummy
+ 0110
cycles
0
1
2
3
Xb
Dummy (ex.: 6)
15 16
Ready for
17 18
XIP
0
19
20
6
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7
4
5
Byte 1
IO switches from Input to Output
21
3
1
2
Sets the Wrap mode
0
22
6
7
4
5
Byte 2
23
3
1
2
0
011
XIP Operations
5
6
7
4
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