n25q064 Numonyx, n25q064 Datasheet - Page 91

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q064 - 1.8V
9.2.3
9.2.4
Note:
DQ0
DQ1
*Address bit A23 is “Don’t Care. ”
C
S
The dummy clock cycle depends on the Fast Read configuration in the NVCR/VCR register (default = 8).
DQ0
DQ1
*Address bit A23 is “Don’t Care.”
C
S
0
Figure 46. Dual Read Serial Flash Discovery Parameter
Dual Command Fast Read (DCFR)
The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI
protocol, parallelizing the instruction code, the address and the output data on two pins
(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read
instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI
protocol, please refer to
Figure 47. Dual Command Fast Read instruction and data-out sequence DIO-SPI
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Instruction
0
1
Instruction
1
2
2
3
3
23 21 19 17
22 20 18 16
4
23 21 19 17
22 20 18 16
4
5
5
6
6
7
24-Bit Address*
7
15 13 11 9
14 12 10 8
24-Bit Address*
8
15 13 11 9
14 12 10 8
8
9 10 11
9 10 11
Section 9.1.6: Dual I/O Fast Read
12 13 14 15
7
6
12 13 14 15
7
6
5
4
5
4
3
2
3
2
1
0
1
0
16 17 18 19 20 21 22 23 24 25 26 27 28
16 17 18 19 20 21 22 23 24 25 26 27 28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Dummy cycles
Dummy cycles
for further details.
7
MSB
6
7
MSB
Data Out 1
6
Data Out 1
5
4
5
4
©2010 Micron Technology, Inc. All rights reserved.
3
2
3
2
1
0
1
0
MSB
6
7
MSB
Data Out n
6
7
4
5
Data Out n
4
5
2
3
2
3
Instructions
0
1
0
1
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