n25q064 Numonyx, n25q064 Datasheet - Page 80

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Instructions
Table 18.
1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
9.1.25
80/154
1
0
1
0
W / VPP
Signal
Status register
DQ0
DQ1
*Address bit A23 is “Don’t Care. ”
C
S
0
0
1
1
SRWD
bit
Protection modes
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 33. Read Lock Register instruction and data-out sequence
format.
0
Software
protected
(SPM)
Hardware
protected
(HPM)
1
High Impedance
Mode
2
Instruction
3
Status register is writeable, if the
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP3,
BP2, BP1, and BP0 bits can be
changed.
Status Register is hardware write
protected. The values in the
SRWD, TB, BP3, BP2, BP1 and
BP0 bits cannot be changed
4
Write protection of the status
5
6
7
MSB
23
register
8
22 21
9 10
24-bit address*
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31 32 33 34 35
2
1
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
0
Protected area
MSB
7
6
Lock Register Out
5
Memory content
4
©2010 Micron Technology, Inc. All rights reserved.
3
(1)
36 37 38
2
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
Unprotected area
1
N25Q064 - 1.8V
0
39
Table 2:
(1)