n25q064 Numonyx, n25q064 Datasheet - Page 75

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

N25Q064 - 1.8V
9.1.20
9.1.21
Note:
Figure 29. Sector Erase instruction sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0)
bits are 0. The Bulk Erase (BE) instruction is ignored if one or more sectors are protected by
the lock register.
Figure 30. Bulk Erase instruction sequence
Program/Erase Suspend
The Program/Erase Suspend instruction allows the controller to interrupt a Program or an
Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input
Page Program, Dual Input Extended Page program, Quad Input Page Program and Quad
Input Extended Page program can be suspended and erased.
Bulk Erase, Write Non Volatile Configuration register and Program OTP cannot be
suspended.
S
C
DQ0
*Address bit A23 is “Don’t Care. ”
S
C
DQ0
0
1
2
Instruction
3
0
4
1
5
2
Instruction
6
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
MSB
23 22
4
8
5
9
24 Bit Address*
6
7
2
29 30 31
1
0
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