n25q064 Numonyx, n25q064 Datasheet - Page 130

• Manufacturer Part Number: n25q064
• Description: 64mb 1.8v, Multiple I/o, 4kb Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

XIP Operations
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Note:
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XIP Operations
XIP (eXecution in Place) is available in each protocol: Extended SPI, DIO-SPI, and QIO-
SPI. XIP allows the memory to be read simply by sending an address to the device and then
receiving the data on one, two, or four pins in parallel, depending on customer
requirements. It offers flexibility to applications, saves instruction overhead, and allows a
reduction to Random Access time. XIP mode can be enabled in two ways:
Setting to 0 bit 3 of the Volatile Configuration Register readies the device to enter XIP mode
right after the next fast read instruction (by 1, 2 or 4 pin). While acting on the Non Volatile
Configuration Register (bit 11 to bit 9, depending on which XIP type is required, single, dual
or quad I/O) the memory enters in the selected XIP mode only after the next power-on
sequence. The Non Volatile Configuration Register XIP configuration bits allows the
memory to start directly in the required XIP mode (Single, Dual or Quad) after the power on.
XIP status must be confirmed forcing the XIP confirmation bit to 0. The XIP confirmation bit
is the value on the DQ0 pin during the first dummy clock cycle after the address in XIP
reading instruction. Forcing bit to 1 on DQ0 during the first dummy clock cycle after the
address (XIP Confirmation bit) returns the memory in the previous standard read mode.
This means it will codify as an instruction code the next byte received on the input pin(s)
after the next chip select. Instead, if the XIP mode is confirmed (by forcing the XIP
confirmation bit to 0), after the device next de-selection and selection cycle, the memory
codify the first 3 bytes received on the inputs pin(s) as a new address. Besides not
confirming the XIP mode during the first dummy clock cycle, it is possible to exit the XIP
mode by mean of a dedicated rescue sequence.
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is
unnecessary to set the Volatile Configuration Register bit 3 to enter XIP; rather, enter XiP
directly by setting XIP Confirmation bit to 0 during the first dummy clock cycle after a fast
read instruction.See
Using the Volatile Configuration Register: this is dedicated to applications that boot in
SPI (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life need to
switch to XIP mode to directly execute some code in the flash.
Using the Non Volatile Configuration Register: this is dedicated to applications that
need to boot directly in XIP.
Section 16: Ordering
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N25Q064 - 1.8V