PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 147

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

15.2.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See
aged Modes”
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in slave mode
• from Idle, in slave or master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the devices
wakes. After the device returns to RUN mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode
TABLE 15-2:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISB
TRISC
SSPBUF
SSPCON1
SSPSTAT
Legend: Shaded cells are not used by the MSSP in SPI mode.
Name
and
OPERATION IN POWER-MANAGED
MODES
SSP Receive Buffer/Transmit Register
data
GIE/GIEH PEIE/GIEL TMR0IE
for additional information.
TRISC7
TRISB7
WCOL
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
—
—
—
to be
Section 19.0 “Power-Man-
TRISB6
TRISC6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
shifted into
TRISB5
TRISC5
SSPEN
RCIE
RCIP
RCIF
Bit 5
D/A
the
TRISC4
TRISB4
SPI
Preliminary
INT0IE
TXIE
TXIP
Bit 4
TXIF
CKP
P
TRISC3
SSPM3
RABIE
SSPIE
SSPIP
SSPIF
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
15.2.9
A Reset disables the MSSP module and terminates the
current transfer.
15.2.10
Table 15-1
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 15-1:
There is also an SMP bit which controls when the data
is sampled.
Bit 3
—
Standard SPI Mode
S
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
PIC18F/LF1XK50
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
shows the compatibility between the
—
SPI BUS MODES
TMR2IF
TMR2IE
TMR2IP
TRISC1
SSPM1
INT0IF
Bit 1
UA
—
CKP
Control Bits State
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
TRISC0
SSPM0
RABIF
Bit 0
DS41350E-page 147
BF
—
CKE
on page
Values
Reset
1
0
1
0
285
288
288
288
288
288
286
286
286