PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 174

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F/LF1XK50
15.3.12
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode
15.3.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23:
FIGURE 15-24:
DS41350E-page 174
Note: T
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
SCL
SDA
WCOL Status Flag
Falling edge of
9th clock
SSPIF
Write to SSPCON2,
BRG
BRG
Acknowledge sequence starts here,
SDA
SCL
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
set PEN
SSPIF set at
the end of receive
BRG
ACKEN = 1, ACKDT = 0
. The SCL pin is then
write to SSPCON2
T
T
(Figure
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
8
D0
15-23).
T
SCL brought high after T
BRG
BRG
Preliminary
)
Cleared in
software
P
T
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
BRG
T
BRG
ACK
15.3.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one T
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A T
cleared and the SSPIF bit is set
15.3.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
PEN bit (SSPCON2<2>) is cleared by
T
hardware and the SSPIF bit is set
BRG
9
BRG
BRG
SSPIF set at the end
of Acknowledge sequence
, followed by SDA = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
 2010 Microchip Technology Inc.
Cleared in
software
BRG
BRG
(Figure
later, the PEN bit is
15-24).