PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 206

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F/LF1XK50
TABLE 16-9:
16.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
DS41350E-page 206
INTCON
PIR1
PIE1
IPR1
RCSTA
TRISC
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
never Idle
Name
Reception”), with the following exceptions:
EUSART Synchronous Slave
Reception
EUSART Transmit Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
(Section 16.4.1.6 “Synchronous
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TRISC5
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Preliminary
TRISC4
CKTXP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
ADDEN
TRISC3
SENDB
BRG16
RABIE
SSPIF
SSPIE
SSPIP
16.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IP
TMR2IF
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
 2010 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR1IP
TRISC0
ABDEN
RABIF
RX9D
TX9D
Bit 0
on page
Values
Reset
288
288
288
287
288
287
287
285
287
287
287