PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 351

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

25.2
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F/LF1XK50 devices also provide
an optional extension to the core CPU functionality.
The
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
TABLE 25-3:
 2010 Microchip Technology Inc.
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
stack space when entering and leaving
subroutines
stack
Mnemonic,
Operands
added
Extended Instruction Set
f, k
k
z
z
k
f, k
k
s
s
features
, f
, z
d
EXTENSIONS TO THE PIC18 INSTRUCTION SET
d
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move z
Move z
Store literal at FSR2,
Subtract literal from FSR
Subtract literal from FSR2 and
decrement FSR2
return
f
z
d
d
include
(destination)
(destination)
s
s
(source) to
(source) to 1st word
Description
eight
2nd word
1st word
2nd word
additional
Preliminary
Cycles
1
2
2
2
2
1
1
2
A summary of the instructions in the extended instruc-
tion set is provided in
are provided in
Set”. The opcode field descriptions in
(page 310) apply to both the standard and extended
PIC18 instruction sets.
25.2.1
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 25.2.3.1 “Extended Instruction Syntax with
Standard PIC18
Note:
Note:
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
MSb
16-Bit Instruction Word
PIC18F/LF1XK50
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
EXTENDED INSTRUCTION SYNTAX
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text
arguments are denoted by braces (“{ }”).
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
Section 25.2.2 “Extended Instruction
Commands”.
and
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
Table
ffkk
11kk
0001
going
25-3. Detailed descriptions
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
LSb
forward,
DS41350E-page 351
Affected
Status
None
None
None
None
None
None
None
None
Table 25-1
optional