PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 321

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
Q1
No
Unconditional Branch
BRA
-1024  n  1023
(PC) + 2 + 2n  PC
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1
2
Read literal
operation
1101
HERE
Q2
No
‘n’
=
=
n
address (HERE)
address (Jump)
0nnn
BRA
operation
Process
Data
Q3
No
Jump
nnnn
Write to PC
operation
Q4
No
nnnn
Preliminary
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
PIC18F/LF1XK50
register ‘f’
Bit Set f
BSF
0  f  255
0  b  7
a [0,1]
1  f<b>
None
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
BSF
Read
1000
Q2
=
=
f, b {,a}
0Ah
8Ah
FLAG_REG, 7, 1
bbba
Process
Data
Q3
DS41350E-page 321
ffff
for details.
register ‘f’
Write
Q4
ffff