PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 239

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

19.4.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the HFINTOSC output is enabled.
The IOSF bit becomes set, after the HFINTOSC output
becomes stable, after an interval of T
the peripherals continue while the HFINTOSC source
stabilizes. If the IRCF bits were previously at a non-
zero value, or INTSRC was set before the SLEEP
instruction was executed and the HFINTOSC source
was already stable, the IOSF bit will remain set. If the
IRCF bits and INTSRC are all clear, the HFINTOSC
output will not be enabled, the IOSF bit will remain clear
and there will be no indication of the current clock
source.
When a wake event occurs, the peripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of T
begins
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
19.5
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
• a Reset
• a Watchdog Time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes
Section 19.3 “Sleep Mode”
Modes”).
 2010 Microchip Technology Inc.
executing
Exiting Idle and Sleep Modes
(see
RC_IDLE MODE
CSD
Section 19.2
following the wake event, the CPU
code
being
and
Section 19.4 “Idle
“Run
clocked
IOBST
. Clocks to
Modes”,
by
Preliminary
the
19.5.1
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The PEIE bIt must also
be set If the desired interrupt enable bit is in a PIE
register. The exit sequence is initiated when the
corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see
A fixed delay of interval T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
19.5.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see
Modes”
device is executing code (all Run modes), the time-out
will result in a WDT Reset (see
dog Timer
The WDT timer and postscaler are cleared by any one
of the following:
• executing a SLEEP instruction
• executing a CLRWDT instruction
• the loss of the currently selected clock source
• modifying the IRCF bits in the OSCCON register
when the Fail-Safe Clock Monitor is enabled
when the internal oscillator block is the device
clock source
and
PIC18F/LF1XK50
(WDT)”).
EXIT BY INTERRUPT
EXIT BY WDT TIME-OUT
Section 19.3 “Sleep
Section 7.0
CSD
following the wake event
Section 24.2 “Watch-
Section 19.2 “Run
DS41350E-page 239
“Interrupts”).
Mode”). If the