PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 277

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

23.0
The PIC18F/LF1XK50 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Full and Underflow
WDT Resets are covered in
Timer
FIGURE 23-1:
 2010 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
(WDT)”.
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections 23.3 and 23.4.
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
V
Detect
Table 23-2
Sleep
DD
WDT
Reset
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
POR Pulse
for time-out situations.
BOREN
Section 24.2 “Watchdog
(2)
1024 Cycles
65.5 ms
Resets”.
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in
23.1
Device Reset events are tracked through the RCON
register
ister indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in
State of
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0
Section 23.4 “Brown-out Reset
(Register
Registers”.
RCON Register
PIC18F/LF1XK50
Figure
“Interrupts”.
23-1). The lower five bits of the reg-
23-1.
S
R
BOR
Section 23.6 “Reset
(BOR)”.
DS41350E-page 277
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in