PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 302
PIC18F-LF1XK50
Manufacturer Part Number
PIC18F-LF1XK50
Description
20-Pin USB Flash Microcontrollers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F-LF1XK50.pdf
(420 pages)
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PIC18F/LF1XK50
24.2
For PIC18F/LF1XK50 devices, the WDT is driven by
the LFINTOSC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the LFINTOSC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
FIGURE 24-1:
DS41350E-page 302
Change on IRCF bits
Note 1: The CLRWDT and SLEEP instructions
All Device Resets
LFINTOSC Source
2: Changing the setting of the IRCF bits of
3: When a CLRWDT instruction is executed,
WDTPS<3:0>
Watchdog Timer (WDT)
clear the WDT and postscaler counts
when executed.
the OSCCON register clears the WDT
and postscaler counts.
the postscaler count will be cleared.
SWDTEN
CLRWDT
WDTEN
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
128
4
Preliminary
Programmable Postscaler
1:1 to 1:32,768
Reset
2010 Microchip Technology Inc.
WDT
Reset
Wake-up
from Power
Managed Modes
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