PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 305

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 24-3:
24.3.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
FIGURE 24-3:
 2010 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Results: All table writes disabled to Blockn whenever WRTn = 0
TBLPTR = 0008FFh
File Name
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 001FFEh
PC = 005FFEh
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTn) DISALLOWED
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
Program Memory
WRTC
Bit 5
Preliminary
—
—
—
—
—
TBLWT*
TBLWT*
Bit 4
—
—
—
—
—
—
instruction that executes from a location outside of that
block is not allowed to read and will result in reading ‘0’s.
Figures
read protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
.
24-3
Bit 3
PIC18F/LF1XK50
—
—
—
—
—
—
Code protection bits may only be written
to a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
through
Configuration Bit Settings
24-5
Bit 2
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
—
—
—
—
—
—
illustrate table write and table
EBTR1
WRT1
Bit 1
CP1
DS41350E-page 305
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—