PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 281

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

23.5
PIC18F/LF1XK50 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
23.5.1
The Power-up Timer (PWRT) of PIC18F/LF1XK50
devices is an 11-bit counter which uses the LFIN-
TOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See
Specifications”
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
TABLE 23-2:
 2010 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
Configuration
2: 2 ms is the nominal time required for the PLL to lock.
Oscillator
Device Reset Timers
POWER-UP TIMER (PWRT)
for details.
TIME-OUT IN VARIOUS SITUATIONS
66 ms
Section 27.0 “Electrical
66 ms
(1)
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
Power-up
OSC
(1)
(1)
(1)
+ 2 ms
OSC
Preliminary
(2)
(2)
and Brown-out
23.5.2
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
23.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.
23.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator
configuration and the status of the PWRT.
Figure
all depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately
useful for testing purposes or to synchronize more than
one PIC18F1XK50/PIC18LF1XK50 device operating in
parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
23-4,
OSC
—
—
—
PIC18F/LF1XK50
OSCILLATOR START-UP TIMER
(OST)
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
OSC
Figure
(2)
23-5,
PLL
) is typically 2 ms and follows
Figure 23-6
Power-Managed Mode
23-3
1024 T
(Figure
1024 T
DS41350E-page 281
through
Exit from
OSC
and
—
—
—
23-5). This is
+ 2 ms
Figure
OSC
Figure 23-7
23-6
(2)
23-3,
also