PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 22

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F/LF1XK50
2.6.1
The HFINTOSC is factory calibrated, but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift,
while giving no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
The operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
REGISTER 2-3:
DS41350E-page 22
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
INTSRC
R/W-0
OSCTUNE REGISTER
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
SPLLEN: Software Controlled Frequency Multiplier PLL bit
1 = PLL enabled (for HFINTOSC 8 MHz only)
0 = PLL disabled
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
100000 = Minimum frequency
• • •
• • •
SPLLEN
R/W-0
OSCTUNE: OSCILLATOR TUNING REGISTER
(Register
W = Writable bit
‘1’ = Bit is set
2-3).
R/W-0
TUN5
R/W-0
TUN4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-
itor (FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and SPLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in
The SPLLEN bit controls the operation of the frequency
multiplier. For more details about the function of the
SPLLEN bit see
Frequency Multiplier”
TUN3
Section 2.5.1
R/W-0
TUN2
Section 2.9 “4x Phase Lock Loop
“LFINTOSC”.
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
TUN1
R/W-0
TUN0
bit 0