PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 23

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

2.7
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-up
Timer (OST). The OST ensures that the oscillator starts
and provides a stable clock to the oscillator module.
The OST times out when 1024 oscillations on OSC1
have occurred. During the OST period, with the system
clock set to the Primary External Oscillator, the program
counter does not increment suspending program
execution. The OST period will occur following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See
Start-up Mode”
FIGURE 2-5:
 2010 Microchip Technology Inc.
New Clk Ready
New Clk Ready
Low Speed
High Speed
System Clock
System Clock
IRCF <2:0>
Note 1: Start-up time includes T
IRCF <2:0>
New Clock
New Clock
Old Clock
Oscillator Start-up Timer
Old Clock
for more information.
Select Old
High Speed
Low Speed
Select Old
CLOCK SWITCH TIMING
Start-up Time
Section 2.12 “Two-Speed
Start-up Time
OST
(1024 T
(1)
Select New
Select New
(1)
OSC
) for external clocks, plus T
Preliminary
Clock Sync
2.8
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1.
2.
3.
4.
5.
6.
7.
Refer to
Clock Sync
SCS<1:0> bits of the OSCCON register are
modified.
The system clock will continue to operate from
the old clock until the new clock is ready.
Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
The system clock is held low, starting at the next
falling edge of the old clock.
Clock switch circuitry waits for an additional two
rising edges of the new clock.
On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
Clock switch is complete.
Figure 2-5
Clock Switching
PLL
PIC18F/LF1XK50
(approx. 2 ms) for HSPLL mode.
for more details.
Running
Running
DS41350E-page 23