PIC18F-LF1XK50 MICROCHIP [Microchip Technology], PIC18F-LF1XK50 Datasheet - Page 256

• Manufacturer Part Number: PIC18F-LF1XK50
• Description: 20-Pin USB Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F/LF1XK50
22.2.3
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
REGISTER 22-3:
DS41350E-page 256
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
Note 1:
Note:
U-0
—
This bit is only valid for endpoints with available Even and Odd BD registers.
USB STATUS REGISTER (USTAT)
The data in the USB Status register is
valid two SIE clocks after the TRNIF inter-
rupt flag is asserted.
In low-speed operation with the system
clock operating at 48 MHz, a delay may
be required between receiving the TRNIF
interrupt and processing the data in the
USTAT register.
Unimplemented: Read as ‘0’
ENDP<2:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
111 = Endpoint 7
110 = Endpoint 6
....
001 = Endpoint 1
000 = Endpoint 0
DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
Unimplemented: Read as ‘0’
U-0
—
USTAT: USB STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
ENDP2
R-x
(Figure
ENDP1
22-3).
R-x
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENDP0
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 6 T
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
FIGURE 22-3:
R-x
Note:
4-Byte FIFO
for USTAT
Data Bus
If an endpoint request is received while
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
DIR
R-x
CY
USTAT from SIE
of clearing TRNIF. If no additional
USTAT FIFO
 2010 Microchip Technology Inc.
x = Bit is unknown
PPBI
R-x
(1)
Clearing TRNIF
Advances FIFO
U-0
—
bit 0