AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 156

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

156
AT91SAM7S32 Preliminary
2. Checking the Main Oscillator Frequency (Optional):
3. Setting PLL and divider:
4. Selection of Master Clock and Processor Clock
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
In some situations the user may need an accurate measure of the main oscillator fre-
quency. This measure can be accomplished via the CKGR_MCFR register.
Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF
field in CKGR_MCFR register. This provides the number of main clock cycles within six-
teen slow clock cycles.
All parameters needed to configure PLL and the divider are located in the CKGR_PLLR
register.
The DIV field is used to control divider itself. A value between 0 and 255 can be pro-
grammed. Divider output is divider input divided by DIV parameter. By default DIV
parameter is set to 0 which means that divider is turned off.
The OUT field is used to select the PLL B output frequency range.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in
the PMC_SR register after CKGR_PLLR register has been written.
Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be
set in the PMC_SR register. This can be done either by polling the status register or by
waiting the interrupt line to be raised if the associated interrupt to LOCK has been enabled
in the PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single
write operation. If at some stage one of the following parameters, MUL, DIV is modified,
LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will
be set again. The user is constrained to wait for LOCK bit to be set before using the PLL
output clock.
Code Example:
If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is
PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set
after eight slow clock cycles.
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is slow clock.
The PRES field is used to control the Master Clock prescaler. The user can choose
between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input
divided by PRES parameter. By default, PRES parameter is set to 1 which means that
master clock is equal to slow clock.
Once PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be
set in the PMC_SR register. This can be done either by polling the status register or by
waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been
enabled in the PMC_IER register.
write_register(CKGR_PLLR,0x00040805)
6071A–ATARM–28-Oct-04