AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 233

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 87. Peripheral Deselection
Mode Fault Detection
SPI Slave Mode
6071A–ATARM–28-Oct-04
Write SPI_TDR
Write SPI_TDR
Write SPI_TDR
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
TDRE
TDRE
TDRE
A
A
A
DLYBCT
DLYBCT
DLYBCT
A mode fault is detected when the SPI is programmed in Master Mode and a low level is
driven by an external master on the NPCS0/NSS signal. As this pin is generally configured in
open-drain, it is important that a pull up resistor is connected on the NPCS0 line, so that a high
level is guaranteed and no spurious mode fault is detected.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read
and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR
(Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
CSAAT = 0
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
PCS = A
A
B
A
AT91SAM7S32 Preliminary
A
A
A
DLYBCT
DLYBCT
DLYBCT
CSAAT = 1
DLYBCS
DLYBCS
PCS = B
PCS = A
A
A
PCS = A
DLYBCS
A
A
B
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