AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 232

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Peripheral Chip Select
Decoding
Peripheral Deselection
232
AT91SAM7S32 Preliminary
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS fields of
the Chip Select Registers have no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined
for each new data.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC
is an optimal means, as the size of the data transfer between the memory and the SPI is either
8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without
reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the
real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode
requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in
the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through
MISO and MOSI lines with the chip select configuration registers. This is not the optimal
means in term of memory size for the buffers, but it provides a very effective means to
exchange data with several peripherals without any intervention of the processor.
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-
DEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select
line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the low-
est numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1)
when not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example,
SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corre-
sponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect
compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
When operating normally, as soon as the transfer of the last data written in SPI_TDR is com-
pleted, the NPCS lines all rise. This might lead to runtime error if the processor is too long in
responding to an interrupt, and thus might lead to difficulties for interfacing with some serial
peripherals requiring the chip select line to remain active during a full set of transfers.
To facilitate interfacing with such devices, the Chip Select Register can be programmed with
the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to
remain in their current state (low = active) until transfer to another peripheral is required.
Figure 87 shows different peripheral deselection cases and the effect of the CSAAT bit.
6071A–ATARM–28-Oct-04