AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 282

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 114. Break Transmission
Receive Break
Hardware
Handshaking
282
Baud Rate
TXEMPTY
US_CR
TXRDY
Clock
Write
TXD
AT91SAM7S32 Preliminary
Start
Bit
D0
D1
D2
STTBRK = 1
D3
The receiver detects a break condition when all data, parity and stop bits are low. This corre-
sponds to detecting a framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit
may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro-
nous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS
pins are used to connect with the remote device, as shown in Figure 115.
Figure 115. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the
USART_MODE field in the Mode Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in
standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as
described below and the level on the CTS pin modifies the behavior of the transmitter as
described below. Using this mode requires using the PDC channel for reception. The transmit-
ter can handle hardware handshaking in any case.
Figure 116 shows how the receiver operates if hardware handshaking is enabled. The RTS
pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full)
coming from the PDC channel is high. Normally, the remote device does not start transmitting
while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls,
indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC
clears the status bit RXBUFF and, as a result, asserts the pin RTS low.
D4
D5
D6
D7
Parity
Bit
Stop
Bit
USART
RXD
TXD
CTS
RTS
Break Transmùission
STPBRK = 1
RXD
TXD
RTS
CTS
Remote
Device
End of Break
6071A–ATARM–28-Oct-04