AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 257

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

TWI Control Register
Register Name:
Access Type:
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a
write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode.
In single data byte master read or write, the START and STOP must both be set.
In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.
In master read mode, if a NACK bit is received, the STOP is automatically performed.
In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.
• MSEN: TWI Master Transfer Enabled
0 = No effect.
1 = If MSDIS = 0, the master data transfer is enabled.
• MSDIS: TWI Master Transfer Disabled
0 = No effect.
1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain
data) are transmitted in case of write operation. In read operation, the character being transferred must be completely
received before disabling.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
6071A–ATARM–28-Oct-04
SWRST
31
23
15
–
–
–
7
30
22
14
TWI_CR
Write-only
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
MSDIS
27
19
11
–
–
–
3
AT91SAM7S32 Preliminary
MSEN
26
18
10
–
–
–
2
STOP
25
17
–
–
9
–
1
START
24
16
–
–
8
–
0
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