AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 376

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

PWM Controller
Operations
Initialization
Source Clock
Selection Criteria
Changing the Duty
Cycle or the Period
376
AT91SAM7S32 Preliminary
Before enabling the output channel, this channel must have been configured by the software
application:
•
•
•
•
•
•
•
•
It is possible to synchronize different channels by enabling them at the same time by means of
writing simultaneously several CHIDx bits in the PWM_ENA register.
•
The large number of source clocks can make selection difficult. The relationship between the
value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can
help the user in choosing. The event number written in the Period Register gives the PWM
accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher
the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be
lower than 1/15 of the PWM period.
It is possible to modulate the output waveform duty cycle or period.
To prevent an unexpected output waveform when modifying the waveform parameters while
the channel is still enabled, PWM_CPRDx and PWM_CDTYx registers are double buffered.
Th e user can write a new pe riod value or du ty cycle value in the upda te re gister
(PWM_CUPDx). This register holds the new value until the end of the current cycle and
updates the value for the next cycle. According to the CPD field in the PWM_CMRx register,
PWM_CUPDx either updates the PWM_CPRDx or PWM_CDTYx.
Configuration of the clock generator if DIVA and DIVB are required
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx
register)
Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing
in PWM_CPRDx Register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained
below.
Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register).
Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation
of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as
explained below.
Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
register)
Enable Interrupts (Writing CHIDx in the PWM_IER register)
Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
In such a situation, all channels may have the same clock selector configuration and the
same period specified.
6071A–ATARM–28-Oct-04