AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 228

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Master Mode
Operations
228
AT91SAM7S32 Preliminary
When configured in Master Mode, the SPI operates on the clock generated by the internal pro-
grammable baud rate generator. It fully controls the data transfers to and from the slave(s)
connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock
signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Reg-
ister, and a single Shift Register. The holding registers maintain the data flow at a constant
rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR
(Transmit Data Register). The written data is immediately transferred in the Shift Register and
transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line,
the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without
reception.
No transfer is started when writing into the SPI_TDR if the PCS field does not select a slave.
The PCS field is set by writing the SPI_TDR in variable mode, or the SPI_MR in fixed mode,
depending on the value of PCS field.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is
completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the
data in SPI_TDR is loaded in the Shift Register and a new transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit
(Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in
SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer
delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of
said delay. The master clock (MCK) can be switched off at this time.
The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit
(Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read,
the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the
Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, no data is loaded in
SPI_RDR. The user has to read the status register to clear the OVRES bit.
Figure 84 on page 229 shows a block diagram of the SPI when operating in Master Mode. Fig-
ure 85 on page 230 shows a flow chart describing how transfers are handled.
6071A–ATARM–28-Oct-04