AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 82

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
Bus Arbiter
Address Decoder
82
AT91SAM7S32 Preliminary
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both
masters.
It is made up of:
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•
•
•
•
The MC handles only little-endian mode accesses. The masters work in little-endian mode
only.
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of
the bus to one of the two masters. The Peripheral Data Controller has the highest priority; the
ARM processor has the lowest one.
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines three separate areas:
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•
•
Figure 29 shows the assignment of the 256-Mbyte memory areas.
Figure 29. Memory Areas
A bus arbiter
An address decoder
An abort status
A misalignment detector
An Embedded Flash Controller
One 256-Mbyte address space for the internal memories
One 256-Mbyte address space reserved for the embedded peripherals
An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that
return an Abort if accessed
14 x 256MBytes
256M Bytes
256M Bytes
3,584 Mbytes
0xF000 0000
0x0000 0000
0xEFFF FFFF
0xFFFF FFFF
0x0FFF FFFF
0x1000 0000
Internal Memories
Peripherals
Undefined
(Abort)
6071A–ATARM–28-Oct-04