AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 45

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

User Reset
Figure 17. User Reset State
6071A–ATARM–28-Oct-04
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
NRST
SLCK
NRST
MCK
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN
in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper
behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-
cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed
high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e N R S T M a n a g e r g u a r a n t e e s t h a t t h e N R S T l i n e i s a s s e r t e d f o r
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
Resynch.
2 cycles
Any
Freq.
Any
>= EXTERNAL RESET LENGTH
Resynch.
2 cycles
XXX
AT91SAM7S32 Preliminary
Processor Startup
= 3 cycles
0x4 = User Reset
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