AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 168

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

PMC Clock Generator PLL Register
Register Name: CKGR_PLLR
Access Type:
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
• DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
168
DIV
0
1
2 - 255
31
23
15
–
7
0
0
1
1
AT91SAM7S32 Preliminary
OUT
Read/Write
OUT
30
22
14
–
6
0
1
0
1
29
21
13
–
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
PLL Clock Frequency Range
Refer to the DC Characteristics section of the product datasheet
Reserved
Refer to the DC Characteristics section of the product datasheet
Reserved
28
20
12
–
4
MUL
DIV
27
19
11
–
3
PLLCOUNT
26
18
10
2
MUL
25
17
9
1
6071A–ATARM–28-Oct-04
24
16
8
0