AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 252

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 93. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 94. Master Write with One Byte Internal Address and Multiple Data Bytes
Figure 95. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
252
TXCOMP
TWD
TWD
TWD
TWD
TWD
TWD
TXRDY
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
S
S
S
AT91SAM7S32 Preliminary
S
Write THR
Write THR
DADR
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
W
the control register starts the transmission. The data is shifted in the internal shifter and when
an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Fig-
ure 94 below). The master generates a stop condition to end the transfer.
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The
RXRDY bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave
address). The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a
slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set
the other slave address bits in the internal address register (TWI_IADR).
W
W
W
A
A
A
A
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
IADR(7:0)
IADR(23:16)
IADR(15:8)
IADR(7:0)
A
A
A
A
IADR(15:8)
A
A
A
IADR(7:0)
S
DADR
IADR(15:8)
DATA
IADR(7:0)
DATA
A
A
R
Write THR
A
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
DATA
S
R
Write THR
A
A
A
N
A
DADR
DATA
P
DATA
P
DATA
DATA
6071A–ATARM–28-Oct-04
R
N
P
N
A
A
A
P
P
P