AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 36

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional Description
Test Pin
Embedded In-
circuit Emulator
Debug Unit
IEEE 1149.1 JTAG
Boundary Scan
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AT91SAM7S32 Preliminary
One dedicated pin, TST, is used to define the device operating mode. The user must make
sure that this pin is tied at low level to ensure normal operating conditions. Other values asso-
ciated with this pin are reserved for manufacturing test.
The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The inter-
nal state of the ARM7TDMI is examined through an ICE/JTAG port.
The ARM7TDMI processor contains hardware extensions for advanced debugging features:
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There are three scan chains inside the ARM7TDMI processor that support testing, debugging,
and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG
port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is
changed.
For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Techni-
cal Reference Manual (DDI0210B).
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blockage of access to the system through the ICE interface.
The Debug Unit can be used to upload an application into the internal SRAM. It is activated by
the boot program when no valid application is detected. The protocol used to load the applica-
tion is XMODEM.
A specific register, the Debug Unit Chip ID Register, gives information about the product ver-
sion and its internal configuration.
The AT91SAM7S32 Debug Unit Chip ID value is 0x27080340 on 32-bit width.
For further details on the Debug Unit, see“Debug Unit (DBGU)” on page 173.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packag-
ing technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE,
EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor
responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not
IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be
performed after JTAGSEL is changed.
In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This
exports the contents of the ARM7TDMI registers. This data can be serially shifted out
without affecting the rest of the system.
In monitor mode, the JTAG interface is used to transfer data between the debugger and a
simple monitor program running on the ARM7TDMI processor.
6071A–ATARM–28-Oct-04